Sensors & Transducers: Data Acquisition Systems and Conversion Unit 4 Part 4

Que4.10. What’s data accession? Give its  factors. 


Data accession( DAQ) 

1. Data accession( DAQ) is the process of measuring an electrical or  physical  miracle  similar as voltage, current, temperature, pressure,  vibration or sound with a computer. 

2. A DAQ system consists of detectors, DAQ  dimension  tackle, and a  computer with  operation software.

1. Detector A detector, also called a transducer, converts a physical   miracle like temperature or vibration, into a measurable electrical  signal like voltage or resistance. 

2. DAQ device A DAQ device acts as the interface between a computer  and signals from the outside world by digitizing incoming analog signals  to be computer readable. DAQ  bias include three  crucial  factors  Signal conditioning circuitry Transforms noisy real- world signals  into forms that can be effectively and directly measured. 

Analog- to- digital transformers( ADCs) Digitize real- world analog  data into digital representations that can be manipulated by computers.  Computer  machine Enables the DAQ device to transmit data to a computer.  exemplifications include USB, PCIe, or Ethernet. 

3. Computer and software A computer with DAQ software is  needed  to reuse,  fantasize, and store  dimension data.  motorist software Gives  operation software the capability to control your  DAQ device with menu- grounded configuration or a programmable API. 

operation software Gives the  stoner a ready- made experience for  acquiring,  assaying, and presenting data. Configuration is done using  menu- grounded interfaces. 

Programming  terrain Allows  druggies to develop their own   operation to acquire,  dissect, and present data, using libraries of  functions( APIs) to  pierce and control their DAQ device. 

Que4.11. Explain analog to digital motor. 

Answer  1. Analog to Digital Converter( ADC) is an electronic intertwined circuit  used to convert the analog signals  similar as voltages to digital or  double  form  conforming of 1s and 0s. 

2. utmost of the ADCs take a voltage input as 0 to 10 V, – 5 V to 5 V,etc.,  and  similarly produces digital affair as some  kind of a  double  number. 

3. Analog to digital motor samples the analog signal on each falling or  rising edge of sample  timepiece. 4.11.1. ADC motor.  Vdd  Analog ADC double affair  signal input 

4. In each cycle, the ADC gets of the analog signal, measures and converts  it into a digital value. 

5. The ADC converts the affair data into a series of digital values by  approximates the signal with fixed  perfection. 

6. In ADCs, two factors determine the  delicacy of the digital value that  captures the original analog signal. These are quantization  position or bit  rate and  slice rate as shown.

7. Bit rate decides the resolution of digitized affair and you can observe as.

2 where 3- bit ADC is used for converting analog  signal. 

9. Assume that one volt signal has to be converted from digital by using  3- bit ADC.  10. thus, a aggregate of 23 =  8 divisions are available for producing 1 V  affair. This results1/8 = 0.125 V is called as  minimal change or  quantization  position represented for each division as 000 for 0 V, 001 for , and likewise upto 111 for 1V. 4.11.2. Analog to digital conversion process.  Ideal transfer  characteristic  Analog  signal  n- bit digital  word  Analog input signal 8/8  Full  scale  Digital  affair  bn  b2  b1  b0  111  110  101  100  011  010  001  000  b2b1b0  ADC 

11. still, 8, 12, If we increase the bit rates like 6., we will get a better   perfection of the signal. 

12. therefore, bit rate or quantization gives the  lowest affair change in the  analog signal value that affect from a change in the digital  representation.

Que4.12. bandy the different types of analog to digital motor. 

Answer  Types of analog to digital transformers  Dual Slope A/ D Converter  1. In this type of ADC motor comparison voltage is generated by using  an integrator circuit which is formed by a resistor, capacitor and   functional amplifier combination. 

2. By the set value of Vref, this integrator generates a sawtooth waveform  on its affair from zero to the value Vref. 

3. When the integrator waveform is started  similarly athwart starts  counting from 0 to 2n – 1, where n is the number of bits of ADC.   

 4. When the input voltage Vin equal to the voltage of the waveform,  also  control circuit captures the counter value which is the digital value of  corresponding analog input value. 

5. This binary  pitch ADC is  fairly medium cost and slow speed device.  timepiece  Control   sense  Counter  in bits)  CLK  CLR  CLK affair  buffer  –  –   D7 D6 D5 D4 D3 D2 D1 D0  Vin  – Vref 4.12.1. Binary  pitch A/ D motor.  Flash A/ D motor 

1. This ADC motor IC is also called as  resemblant ADC, which is a most  extensively used effective ADC in terms of its speed. 

2. This flash analog to digital motor circuit consists of a series of  comparators where each one compares the input signal with a unique  reference voltage. 

3. At each comparator, the affair will be high state when the analog input  voltage exceeds the reference voltage. 

4. This affair is further given to precedence encoder for generating  double   law grounded on advanced order input  exertion by ignoring other active inputs.  This flash type is a high- cost and high- speed device. ? ? ? ?  Input analog voltage  Reference voltage V1.0 V  V  R  R  R  R  V  V 4.12.2. Flash A/ D motor. 

Successive approximation A/ D motor 

1. The SAR ADC is a  ultramodern ADC IC and  important faster than binary  pitch and  flash ADCs since it uses a digital  sense that converges the analog input  voltage to the closest value. 

2. This circuit consists of a comparator, affair latches,  consecutive  approximation register( SAR) and D/ A motor.  Control  sense  consecutive  approximation  register  Digital to analogue  motor  Comparator  Analogue input  –  4.12.3. Consecutive approximation A/ D motor. 

3. At the  launch, SAR is reset and as the LOW to HIGH transition is introduced,  the MSB of the SAR is set. 

4. also this affair is given to the D/ A motor that produces an analog   fellow of the MSB, further it’s compared with the analog input Vin. 

5. still,  also MSB will be cleared by the SAR,  If comparator affair isLOW.otherwise the MSB will be set to the coming position. 

6. This process continues till all the bits are tried and after Q0, the SAR  makes the  resemblant affair lines to contain valid data. 

Que4.13. Give the  operations of ADC. 

Answer  1. They’re used in computer to convert the analog signal to digital signal. 

2. They’re used in cell phones. 

3. They’re used in microcontrollers. 

4. They’re used in digital signal processing. 

5. They’re used in digital  storehouse oscilloscopes. 

6. They’re used in scientific instruments. 

7. They’re used in music  reduplication technologyetc. 

Que4.14. Explain Digital to Analog Converter( DAC).   

Answer  1. Digital to Analog Converter( DAC) is a device that transforms digital  data into an analog signal. 

2. According to the Nyquist- Shannon  slice theorem, any  tried  data  can be reconstructed  impeccably with bandwidth and Nyquist criteria. 

3. A DAC can reconstruct  tried  data into an analog signal with  perfection. 

4. The digital data may be produced from a microprocessor, operation  Specific Integrated Circuit( ASIC), or Field Programmable Gate Array ( FPGA), but eventually the data requires the conversion to an analog  signal in order to interact with the real world. 

Que4.15. bandy the different types of Digital to Analog Converter  DAC). 

Answer  There are two  styles generally used for digital to analog conversion  R- 2R graduation network  system 

1. The R- 2R graduation DAC constructed as a  double- weighted DAC that uses  a repeating protruded structure of resistor values R and 2R. 

2. This improves the  perfection due to the relative ease of producing equal  valued-betrothed resistors( or current sources). 

3.Fig.4.15.1 shows the 4- bit R- 2R graduation DAC. In order to achieve highlevel   delicacy, we’ve chosen the resistor values as R and 2R. 

4. Let the  double value b3b2b1b0, if b3 =  1, b2 =  b1 =  b0 =  0,  also the simplified  form ofFig.4.15.1 DAC circuit is shown inFig.4.15.2. The affair voltage  is V0 =  3R( i3/ 2) =  Vref/ 2. 

5. also, If b2 =  1, and b3 =  b1 =  b0 =  0,  also the affair voltage is  V0 =  3R( i2/ 4) =  Vref/ 4 and the simplified circuit is shown inFig.4.15.3. 

6. still,  also the simplified form of Fig, If b1 =  1 and b2 =  b3 =  b0 =  DAC circuit is shown inFig.4.15.4. The affair voltage is  V0 =  3R( i1/ 8) =  Vref/ 8. 

7. Eventually, the circuit is shown inFig.4.15.5 corresponding to the case  where b0 =  1 and b2 =  b3 =  b1 =  0. The affair voltage is V0 =  3R( i0/ 16) =   Vref/

16.  Weighted resistors  system 

1. The  introductory operation of DAC is the capability to add inputs that will eventually  correspond to the  benefactions of the  colorful bits of the digital input. 

2. In the voltage  sphere, that’s if the input signals are voltages, the  addition of the  double bits can be achieved using the flipping summing  amplifier as shown. 

3. In the voltage  sphere, that’s if the input signals are voltages, the  addition of the  double bits can be achieved using the flipping summing  amplifier. 

4. The input resistors of the op- amp have their resistance values  ladened  in a  double format. 

5. When the  entering  double 1 the switch connects the resistor to the  reference voltage. 

6. When the  sense circuit receives  double 0, the switch connects the resistor  to base. All the digital input bits are  contemporaneously applied to the  DAC. 

7. The DAC generates analog affair voltage corresponding to the given  digital data signal. 

8. For the DAC the given digital voltage is b3, b2, b1, b0 where each bit is a   double value( 0 or 1). The affair voltage produced at affair side is,  V0 =  R0/ R( b3 b2/ 2 b1/ 4 b0/ 8) Vref 

9. As the number of bits is  adding  in the digital input voltage, the range  of the resistor values becomes large and consequently, the  delicacy  becomes poor.

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